Chapter 5. Computing with Register Machines

5.1. Designing Register Machines

1. A Language for Describing Register Machines (exercise 5.1, exercise 5.2)

2. Abstraction in Machine Design (exercise 5.3)

3. Subroutines

4. Using a Stack to Implement Recursion (exercise 5.4, exercise 5.5, exercise 5.6)

5. Instruction Summary

5.2 A Register-Machine Simulator

1. The Machine Model (exercise 5.7)

2. The Assembler (exercise 5.8)

3. Generating Execution Procedures for Instructions (exercise 5.9, exercise 5.10, exercise 5.11, exercise 5.12, exercise 5.13)

4. Monitoring Machine Performance (exercise 5.14, exercise 5.15, exercise 5.16, exercise 5.17, exercise 5.18, exercise 5.19)

5.3 Storage Allocation and Garbage Collection

1. Memory as Vectors (exercise 5.20, exercise 5.21, exercise 5.22)

2. Maintaining the Illusion of Infinite Memory

5.4 The Explicit-Control Evaluator

1. The Core of the Explicit-Control Evaluator
2. Sequence Evaluation and Tail Recursion

3. Conditionals, Assignments, and Definitions (exercise 5.23, exercise 5.24, exercise 5.25)

4. Running the Evaluator (exercise 5.26, exercise 5.27, exercise 5.28, exercise 5.29, exercise 5.30)

5.5 Compilation

1. Structure of the Compiler (exercise 5.31, exercise 5.32)

2. Compiling Expressions
3. Compiling Combinations
4. Combining Instruction Sequences

5. An Example of Compiled Code (exercise 5.33, exercise 5.34, exercise 5.35, exercise 5.36, exercise 5.37, exercise 5.38)

6. Lexical Addressing (exercise 5.39, exercise 5.40, exercise 5.41, exercise 5.42, exercise 5.43, exercise 5.44)

7. Interfacing Compiled Code to the Evaluator (exercise 5.45, exercise 5.46, exercise 5.47, exercise 5.48, exercise 5.49], [[Exercise5-50, exercise 5.51, exercise 5.52)